Challenge-response based secure test wrapper for testing cryptographic circuits

C ryptographic circuits need special test infrastructure due to the concern of security involved. Normal design for testability methods, such as scan chains, as applied to most ASICs cannot be applied directly to Cryptographic chips. These methods, though providing the highest testability, open backdoors or side-channels for attackers, to extract secret keys or Intellectual Property information from the core. Built-in Self-Test is normally applied for such secure chips, but it suffers from aliasing, high area overhead, and inadequate fault coverage, requiring additional deterministic top-up test patterns. Existing secure testing methods only provide security through obscurity by randomizing the scan chain operation. The current work seeks to address this tradeoff between security, testability and test area overhead by presenting a challenge-response based Secure Test Wrapper structure, suitable for testing IP cores in a SoC environment. This scheme includes the KATAN lightweight block-cipher into IEEE 1500 Standard Test Wrapper and as such provides an extremely compact locking and unlocking mechanism for the standard scan chains. The overhead to include this secure locking/unlocking mechanism is limited to about 9% compared to a standard scan and test wrapper. The main contributions of the paper are full testability, very high security and scalability of the proposed design.